Multi-core and many-core heterogeneous computing systems (MMCHCS) recently are widely used in networking, mobile systems such as mobile phones, PDAs and even subnotebook computers. These systems contain two types of processor cores: usual cores intended for high performance operation and low power cores intended for power aware operation. The cores of second type allow cut up energy consumption of computing system in cases when it is possible. This also leads to decreasing of power consumption of computing systems and allows prolong a battery life in mobile systems without recharging. Very often all cores or processors are located on the same chip and in this case these systems are known as system-on-chip (SoC) computing systems. The usual system software using for operation of MMCHCS consist of compiler and scheduler. The compiler is responsible for creation of program running on such devices and the scheduler is responsible for loading of such devices on run-time. The main question in software development for these systems is in solution of problem what kind of core should be used for operation of current program block in MMCHCS. In all modern compilers this solution is made by programmer so-called manually. This means that every programmer following to his own ideas about prediction of efficiency of MMCHCS decides what kind of cores he will use for running of current block of his program and rigidly assigns current block to core type in his program by himself so-called manually.
During the following run of the program it is not possible to change this assignment by any manner. The modern schedulers can't change this politics also. This follows to the loss of efficiency of MMCHCS due to unbalancing of computations.
Each program 100 consists of sequential blocks 101, 105, 109 as shown in FIG. 1. The first and the last blocks 101, 109 are always sequential, but all other intermediate blocks 103, 105, 107 can be sequential, parallel or massive parallel.
The difference between parallel 103 and massive parallel 107 blocks lies in the number of parallel loops when the parallel block 103 is running on specified cores. For example, if a parallel block 103 has 8 loops and the computing system contains 8 available cores, then this block will be parallel or simple parallel, but not massive parallel, because all loops can be loaded into the cores at once. If there are 8 loops, but on the system with only 2 available cores, then there is a massive parallel block, because it needs 4 times to load all loops.
The following definition of massive parallel blocks is used in the following. There are K cores or processors and N parallel loops in block. Then if N/K>3, the considering block is massive parallel. Otherwise the block is a simple parallel or parallel. Thus if all available loops can be loaded in 1, 2 or 3 times, then the considering parallel block is simply parallel or parallel. Otherwise, then it needs 4, or more times to load all available loops by loops of parallel block, there is a massive parallel block.
Currently used multi-core and many-core heterogeneous computing systems (MMCHCS) are static with respect to scheduling program blocks to processor cores. Partitioning of the workload for CPU is static and cannot be dynamically changed, in particular static load balancing schemes are used and background tasks are not monitored. Currently used MMCHCS systems are inflexible and user unfriendly.